CHAPTER # 14 PROCESSOR STRUCTURE AND FUNCTIONS

Q# 07

Consider the timing diagram of Figures 12.10. Assume that there is only a two-stage pipeline (fetch, execute). Redraw the diagram to show how many time units are now needed for four instructions.

SOLUTION:

                                                          TIME

INSTRUCTIONS	1	2	3	4	5
INS 1	F	E
INS 2		F	E
INS 3			F	E
INS 4				F	E

Q#8

Assume a pipeline with four stages: fetch instruction (FI), decode instruction and calculate addresses (DA), fetch operand (FO), and execute (EX). Draw a diagram similar to Figures 12.10 for a sequence of 7 instructions, in which the third instruction is a branch that is taken and in which there are no data dependencies.

SOLUTION:

                            TIME                                                       BRANCH PENALTY

INSTRUCTIONS	1	2	3	4	5	6	7	8	9	10
I1	FI	DA	FO	EX
I2		FI	DA	FO	EX
I3			FI	DA	FO	EX
I4				FI	DA	FO
I5					FI	DA
I6						FI
I15							FI	DA	FO	EX

Q# 09

 A pipelined processor has a clock rate of 2.5 GHz and executes a program with 1.5 million instructions. The pipeline has five stages, and instructions are issued at a rate of one per clock cycle. Ignore penalties due to branch instructions and out of-sequence executions.
a. What is the speedup of this processor for this program compared to a non pipelined processor, making the same assumptions used in Section 12.4?

SOLUTION:

No. of instructions (n) =1.5 million

1 Million=10⁶

No. of  stages in pipleline ( k)=5

Instructions rate per clock cycle=1

Torque (τ)=1

Speed up=?

S= [ nk ] τ / [k+ (n-1)] τ

s= (1.5 x 10⁶  ) (1) / 1+(1.5 x 10⁶-1)

s= 1
b. What is throughput (in MIPS) of the pipelined processor?

SOLUTION:

MIPS rate=?

No. of instructions=1.5 million

MIPS=  Ic / T x 10 ⁶

T= nk

  = (1.5)(5)

T =7.5

MIPS=  1.5 x 10⁶/7.5 x 10 ⁶

MIPS=  0.2

Q# 10

A non-pipelined processor has a clock rate of 2.5 GHz and an average CPI (cycles per instruction) of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to 2 GHz.
a. What is the speedup achieved for a typical program?

SOLUTION:

No. of  stages in pipeline( k)=5

SUPPOSE  THAT: n= 100

Speed up= [nk] τ/[k+(n-1)] τ

S= (100)(5) / 5 + (100-1)

  =500 /104

  S=4.8

b. What is the MIPS rate for each processor?

SOLUTION:

MIPS=?

Clock Rate (non-pipelined) = 2.5GHz

CPI= 4

Clock rate (pipelined ) =2GHZ

MIPS for non-pipelined:

MIPS = Clock rate / CPI

MIPS = 2500 MHz/4

 MIPS=625

MIPS for pipelined:

CPI=1, because instructions are completed at the rate one per clock cycle.

MIPS = Clock rate / CPI

MIPS = 2000 MHz/1

MIPS = 2000